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A closed loop brain computer interface system: Hardware implementation
A high data rate wireless brain computer interface
A low power communication protocol for physiological sensors
A novel method of rational function approximation using orthogonalized polynomials with real coefficients
A novel wideband stepped impedance filter for suppression of common-mode noise in differential lines
A reconfigurable hardware implementation for the principal component analysis
Accelerating data center applications through energy-efficient reconfigurable computing: From near-data processing to data-access reduction
Architectural design space exploration of reciprocal and square root for arbitrary precision fixed-point and floating-point arithmetic
Characteristics and bounds of spline interpolation using forward distance
Development of decomposition model for improving signal progression efficiency in urban network
Effect of green compact density on 3NI-AL and 3NI-AL-CNT composite synthesis through electro-thermal explosion
Efficient hardware implementation of compressed sensing algorithm for neural spikes
Filled-cavity resonator method for complex permittivity measurement
I/O characteristics of smartphone applications and their implications for eMMC design
I/O stack optimization for non-volatile memory based storage systems
Learning data augmentation policies for image classification
Machine learning techniques for automatic modulation classification
Multi sensor reconfigurable physiological signal monitoring system
Non-intrusive activity and presence detection for multiple people using low resolution ambient sensors
Optimization of electronic speed controller (ESC) power quality

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