Many algorithms rely on floating point arithmetic for the dynamic range of representations and require millions of calculations per second. The floating point unit generation approach allows for the creation of floating point units with differing throughput, latency, and area characteristics. In floating point arithmetic, addition is most complicated operation which offers major delays as taking significant area. Most commercial and academic floating point libraries have developed vast collection of floating adder algorithms with differing overall latency and area. Floating point adder offers large area and lower performance. Latency and area is main focus of our research towards studying and implementing floating point addition algorithm. Proposed adder design based on close-far path algorithm. Simultaneously two floating additions are performed in close and far data paths using interval addition approach. Further improvement in latency is done by pipelined architecture. By utilizing operands in data path variable latency is achieved. Proposed adder design and synthesized onto TSMC 0.18 micron technology. Algorithm's sub -operation is optimized for area and time. Each sub -operation is design and synthesized onto TSMC 0.18 Micron devices.