Description
Multiplication and Squaring functions are widely used in many real time applications. They form an integral part in implementation of many Digital Signal Processing, Digital Image Processing and Multimedia algorithms. The size and power consumption of a DSP chip is influenced by the multiplication and squaring architectures that are used. The aim of this research is to propose a novel fixed width parallel array multiplier. The proposed approach is aimed at providing a degree of flexibility to designers when it comes to designing fixed width multipliers with reduced errors and smaller chip area. The design being proposed, uses a technique known as pre-truncation where in the inputs to the multiplier are truncated before generating the partial product array. The partial product array is further truncated to generate an output that is N bits wide, where N is the input data size. Truncation, results in errors and the proposed design uses correction techniques based on mathematical equations to offset these errors. The design is very flexible as varying order of area savings can be achieved by varying the input bit truncation. The design being proposed was implemented in Verilog and the area report generated. For N=10 and input truncation set to 5 bits, the proposed design resulted in an area of 1797.122 _m^2 which is much smaller than a Dual Tree Multiplier(2573.830_m^2) of same input data size. Simulations were carried out in MATLAB to generate error results. The maximum and mean error of the proposed multiplier for N=10 and truncation set to 2 bits is 4.000977 and 6.71524 respectively. This is comparable to the maximum and mean error of the Dual Tree Multiplier which is 2.055664 and 4.094468 respectively. The details of the results, including the area and error, are discussed in this thesis.
