Description
Fast Fourier Transform (FFT) is one of the most important algorithms in digital signal processing. FFT is widely used algorithm in various areas like image and speech processing, medical electronics and telecommunication. Design of FFT processor requires better approach, as growing the need of faster and small battery operated devices. Micropipelined design has many advantages over the synchronously pipelined design in terms of area, latency and power consumption. FFT processor does lots of complex additions and multiplications. We remarks that first two stages of FFT computation have all the trivial multiplications where one or both of the multiplicand and multiplier are 0, 1 or -1. We have proposed a low latency multiplier, which is disable a power hungry multiplier in trivial case and directly compute multiplier's output. Our proposed control circuit for handshaking do not require bounded delay element, so it helps to improve latency and area of the micropipelined FFT processor. Our designed 8- point micropipelined FFT processor computes all stages in 15 clock cycles and having 273.5 MHz maximum clock frequency.
