For an efficient design of RF integrated circuits (RFICs), accurate and robust device models are necessary. The models are required for active devices, like transistors or diodes and passive components, like inductors or capacitors. The device models are obtained by characterization of devices on a wafer; such models are hard to obtain in technologies like CMOS due to high substrate losses and low interconnect conductance. In this thesis, a novel de-embedding approach is proposed to characterize the devices in CMOS technology. The proposed de-embedding procedure is based on (1) using a shield based on-wafer test-fixture, (2) estimation of probing pad parasitics using in-fixture standard measurements and (3) modeling of remaining parasitics using the transmission line models. The method can even be extended to de-embed the parasitics of other similar test-fixtures which hold arbitrarily sized devices. The entire de-embedding method makes use of just one in-fixture standard that has physically to be built on a wafer. Several on-wafer test fixtures and the de-embedding standards are built and measured. The validity of the proposed method is evaluated with device S-parameter results calculated from industry standard 4SD (4-step de-embedding) technique, as well as from 3D-electromagnetic simulations. On-wafer S-parameter measurements for test fixtures along with device under tests have been carried out up to 10 GHz of frequency. This method of de-embedding saves significant amount of probing time and die space on a wafer; and hence reduced costs. All the required test structures for the project are fabricated on top of a silicon substrate using double ploy-three metal layer in 0.5_m CMOS technology with the assistance MOSIS research educational program.