Description
Direct Digital Frequency Synthesizers provide a means to produce sinusoidal waveforms from a single source signal, the system clock. They yield an extremely efficient solution to creating a waveform or waveforms of high spectral purity and high resolution. The designs can be found in many digital communication and radar systems This thesis investigates some of the state-of-the-art methods for implementing Direct Digital Frequency Synthesizers (DDFS) via polynomial interpolation over segmented phase values. Introduced is a novel DDFS interpolated by a quasi-linear polynomial over non-uniform segmentation. This is done by breaking the cosine wave into segments with nonuniform lengths. Each segment is approximated by either a linear or depressed parabolic polynomial. More specifically, when the sinusoid is at a max, a depressed parabola is used to model the shape rather than linear segments. This has reduced the approximation error compared to pure linear interpolation. The next step is to implement the design in hardware to evaluate its performance (power consumption and speed). The output spectrum is analyzed and the variable of interest (to be maximized) is the Spurious Free Dynamic Range (SFDR) or ratio of the fundamental harmonic amplitude to that of the next greatest harmonic. The SFDR is calculated and designed for in MATLAB. The system is then modeled using Simulink where the SFDR of the output waveform is confirmed. The design is then implemented in both forms of electronic design: FPGA and ASIC. The modeled system is converted to Verilog hardware description language and implemented on FPGA using the Xilinx ISE Design Suite 13.4 and the Virtex-5 design kit. Additionally, the system is implemented for ASIC using Cadence Encounter to analyze chip size and power requirements
