The electronic devices for area- and power-constrained applications, such as brain-implantable devices, pose serious limitations and challenges on both the algorithms that can be realized on such devices, as well as novel architectural designs. This thesis presents the design and implementation of various efficient hardware architectures for neural signal processing. The hardware architectures were implemented in both field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs), while meeting strict application constraints. The characteristics and implementation results of the proposed novel designs are compared against comparable state-of-the-art circuits to quantify the resource utilization, power consumption, and processing performance of the designed hardware architectures.
