Application-specific instruction set processors (ASIPs) are the programmable processors optimized for a specific application. This thesis demonstrates how ASIPs can provide efficient solutions in the Wireless Communications Technology. A general-purpose MIPS (microprocessor without interlocked pipeline stages) pipelined processor is first designed and verified in Verilog HDL as a foundation for this thesis. The processor is then enhanced to support hazard detection and forwarding operations. The final goal of the thesis is to demonstrate ASIPs capability in supporting applications like quadrature amplitude modulation (QAM) and multiple-input multiple-output (MIMO). These applications were first simulated to identify ASIP optimizations. Fixed-point arithmetic with Newton-Raphson division were identified as needed in order to support these applications. The processor is enhanced to support these two operations. QAM decoder is successfully programmed on the processor and results are verified. Matrix operations for MIMO are explored and programmed as functions in the processor instruction memory. This also includes blockwise analytical matrix inversion algorithm. 2_2 MIMO MMSE receiver is mapped on this application-specific instruction set processor and results are verified for accuracy and performance.
