A fractional delay filter is a digital filter having the main function so as to delay the processed input signal as a fraction of the sampling period time. Fractional delay digital filters using the Farrow structure provide an efficient solution when real-time and variable delay of signals are required. Given the limited speed and number of multipliers on field-programmable gate arrays (FPGAs), this thesis presents an efficient implementation of Farrow structure using the sum-of-powers-of-two (SOPOT) numerical representation of the filter coefficients. An algorithm for generating the canonical-signed-digit (CSD) numbers from their two's complement equivalent and designing the Farrow coefficients in SOPOT form is presented. Using the SOPOT representation, multiplication by constant values can be implemented with a relatively small number of shift and addition operations. Moreover, intermediate operations can be shared among different multiplications by constant values with the help of multiplier blocks (MBs). Further optimization of the fractional delay filter is done by using sub-expression elimination and cut-set retiming. Another goal of the thesis is to efficiently implement fractional delay filters for sample rate conversion. The need for non-integer sampling rate conversion appears when the two systems operating at different sampling rates have to be interfaced. Efficient fractional sampling rate converters based on the FIR filters and the polyphase decomposition are presented. The performance of Farrow filter which supports continuously variable resampling is also discussed. A digitally-controlled sample data line is implemented with recursive all-pass filter sections. A high performance polyphase IIR filter is implemented with very low FPGA resource requirements. Our simulation and implementation results show that the proposed approach can greatly reduce the hardware complexity when compared to the other state-of-the-art implementations.