We've Moved!
Visit SDSU’s new digital collections website at https://digitalcollections.sdsu.edu
Description
Hardware optimization of design implementation is one of the major issues in today’s growing world technology, which includes reduction in integrated circuit area, computational workload and power consumption. This thesis is divided into two main parts, both shows various methodologies in filter architectures implementation. The first part includes four different modeling approach of infinite impulse response (IIR) filters, in which two of them show the all-pass polyphase recursive filter and the other two show the narrow bandwidth low-pass polyphase recursive filters. Both uses the first and second order all-pass prototype to build filter functionality. Research includes the hardware implementation characteristics, such as performance of the architecture which depends on the chosen filter structure. The second part of the thesis shows the multi-rate filtering techniques used to process signals with large ratio of sample rate to bandwidth. In this design, input port polyphase filter is used for the reduction of the sample rate and output polyphase port can be used to increase the same. The main inspiration for this multirate filter design is the significant reduction in computational processing load. The standard relation between coefficient bit-widths and spectral stop-band attenuations are given by this study of polyphase all-pass recursive filters (PARF). By using the technique of lower sample rate at specification (inner stage) filter we can save computational resources. This technique can have more than one down-sampling and up-sampling stages. Inner filter stage can be a single stage or M-path filter. With this option we can reduce the overall workload. We also discussed the same example for PARF without commutator. Hardware implementation results of various structures run on a Xilinx virtex Field Programmable Gate Array (FPGA) and were obtained by a synthesizing verilog descriptions.
