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Cascade Analysis Synthesis Channelizer Structures For Reduced Computational Work Load
Harris, Fredric J.Nagaraj, SantoshPaolini, Christopher P
xii, 49 pages : illustrations
As the data rates of today's communication systems increases, a need for more efficient data processing algorithms becomes more important. This importance comes around because of several underlying challenges that are faced by equipment manufacturers, since they are the ones who strive to build their products using minimal resources to reduce cost while guaranteeing performance and design requirements. A DSP processor is limited many factors, two of which are important to the subject of this thesis are, the number of instructions it can perform per second, and the amount of memory it has. In order for a DSP processor to be able to handle the processing of a wide band signal it has to be of high speed. This thesis contains an investigation of the computational efficiency of a channelizer design to handle wide band signals and control the bandwidth with different granularities and transition band control, using the minimum number of operations that a processor needs to perform. The subject of Multi-Rate Signal processing constitutes the foundation of this work, along with the efficient design of digital filters. Two system designs of Analysis and Synthesis channelizers are presented, then a comparison is made between the two designs in terms of the impulse response of the two designs and the number of multiplies and adds. An introduction to efficient digital filter design is presented first, the design of polyphase filters for up-sampling and down-sampling is discussed, then the comparison is made for different design structures is made with simulation results to back up the conclusion.
Includes bibliographical references (page 49).
Electrical and Computer Engineering
Master of Science (M.S.) San Diego State University, 2015
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