Principal component analysis (PCA) is one of the efficient techniques for the dimensionality reduction in multivariate analysis. The efficient hardware implementation of the PCA system with lower latency can find its application in many real-time signal processing systems. The main focus of this thesis is to develop a high-throughput hardware architecture for the PCA system. The developed PCA reconfigurable architecture includes both, learning and mapping phases of the PCA system. The designed PCA includes various computational units, such as the mean calculator, covariance matrix computation, eigen solver, sorter, and supports input data sets with parameterizable dimensions. We model our proposed PCA architecture in both floating-point and fixed-point representations using our custom-developed library of numerical operations in MATLAB. The synthesizable model of the PCA design is modeled in Verilog hardware description language and its cycle-accurate bit-true simulation results are verified against its fixed-point simulation model. The PCA hardware is implemented on a field-programmable gate array (FPGA) and its ASIC implementation results in a standard 45-nm CMOS process are obtained. The characteristics and implementation results of the implemented PCA system are compared with the other published work.
