Description
Non-coherent impulse-radio ultra-wideband (IR-UWB) transceivers are attractive candidates for applications where silicon area and power consumption are relatively limited. This thesis presents the compact digital architecture design and implementation of a non-coherent IR-UWB transceiver based on the energy detection scheme, including the synchronizer module. This thesis also presents the first compact hardware implementation of a code-shifted reference (CSR) UWB transceiver. The security of the transmission is based on changing the physical properties of the transmission without the use of higher level security options. The software models of the designed transceivers are simulated and verified in both floating-point and fixed-point numerical representations. The synthesizable Verilog descriptions of both transceiver architectures are simulated and verified against their fixed-point simulation models. The transceivers are implemented on our custom-developed field-programmable gate array (FPGA) board. The bit error rate performance of the transceivers is measured in real-time on the FPGA, utilizing an accurate on-chip Gaussian noise generator. The characteristics and implementation results of the transceiver architectures on the FPGA are presented. An ASIC architecture of the IR-UWB transceiver is estimated to occupy 0.035287 mm2 and dissipate 2.232 mW from a 1.1-V supply while operating at 230 MHz in a standard 45-nm CMOS technology. An ASIC architecture of the CSR-UWB transceiver is estimated to occupy 0.035651 mm2 and dissipate 2.706 mW from a 1.1-V supply while operating at 223 MHz in the same standard 45-nm CMOS technology.
